Field of the Invention
The present invention relates generally to processors, and in particular to methods and mechanisms for maintaining an order of instructions in relation to barriers within a processor.
Description of the Related Art
In modern day processors, instructions may be executed out of order. This may improve processor performance, but it may also result in unintended behavior. For example, a programmer may intend for specific sequences of instructions to execute in order, and if the processor reorders these instructions, unwanted errors may occur as a result. Therefore, to avoid these errors, barrier commands may be inserted into the code to enforce an instruction order. A barrier has a property such that instructions that the barrier controls must not be reordered with respect to the barrier. Therefore, the barrier can be inserted into a stream of instructions to prevent some instructions from being executed before other instructions.
Some processors include multiple independent reservation stations for issuing operations to be executed. It may be difficult to enforce an order for operations issued out of the multiple reservation stations. In other words, keeping track of which operations were before a barrier and which operations were after a barrier can be challenging, especially for operations in a first reservation station when the barrier is in a second reservation station.